`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// //PCI bus analyzer. Never started, really. Just has some block ram set up. //////////////////////////////////////////////////////////////////////////////// module analyzer(ib_data, ib_addr, ib_read_in, ib_write_in, ib_clock, pci_clock, pci_ad, pci_cbe, pci_trdy, pci_irdy, pci_frame, pci_devsel, pci_idsel, reset, ib_pci_req); inout [15:0] ib_data; input [10:0] ib_addr; input ib_read_in; input ib_write_in; input ib_clock; input ib_pci_req; input pci_clock; input [31:0] pci_ad; input [3:0] pci_cbe; input pci_trdy; input pci_irdy; input pci_frame; input pci_devsel; input pci_idsel; input reset; wire [15:0] ram_data_0; wire [15:0] ram_data_1; reg [15:0] data_out_latch; reg [10:0] ib_addr_latch; reg [7:0] capture_pci_addr; reg [2:0] capture_state; reg analyzer_run; reg [18:0] pci_base_addr; parameter MEMREAD = 4'b0110; parameter MEMWRITE = 4'b0111; parameter CFGREAD = 4'b1010; parameter CFGWRITE = 4'b1011; wire cfg_hit = ((pci_cbe == CFGREAD || pci_cbe == CFGWRITE) && pci_idsel && pci_ad[1:0] == 2'b00); wire addr_hit = ((pci_cbe == MEMREAD || pci_cbe == MEMWRITE) && pci_ad[31:13] == {pci_base_addr}); wire hit = (cfg_hit || addr_hit) && ~pci_frame; always @ (posedge pci_clock or posedge reset) if(reset) begin capture_pci_addr <= 0; capture_state <= 0; end else begin case(capture_state) 0: if(hit && analyzer_run)begin capture_pci_addr <= capture_pci_addr + 1; capture_state <= 1; end 1: begin capture_pci_addr <= capture_pci_addr + 1; if(pci_frame) capture_state <= 2; end 2: begin capture_pci_addr <= capture_pci_addr + 1; capture_state <= 3; end 3: begin capture_pci_addr <= capture_pci_addr + 1; capture_state <= 0; end endcase end //a capture buffer RAMB4_S16_S16 capture_buffer0( .CLKA(ib_clock),.RSTA(reset), .ENA(1'b1),.WEA(ib_write & (ib_addr[10:8] == 3'b001)), .ADDRA(ib_addr[7:0]),.DIA(ib_data),.DOA(ram_data_0), .CLKB(pci_clock),.RSTB(reset), .ENB(analyzer_run || capture_state != 0),.WEB(1'b1), .ADDRB(capture_pci_addr[7:0]), .DIB({pci_cbe[3:0],pci_trdy,pci_irdy,pci_frame,pci_devsel,pci_idsel,pci_ad[22:16]}), .DOB() ); RAMB4_S16_S16 capture_buffer1( .CLKA(ib_clock),.RSTA(reset), .ENA(1'b1),.WEA(ib_write & (ib_addr[10:8] == 3'b010)), .ADDRA(ib_addr[7:0]),.DIA(ib_data),.DOA(ram_data_1), .CLKB(pci_clock),.RSTB(reset), .ENB(analyzer_run || capture_state != 0),.WEB(1'b1), .ADDRB(capture_pci_addr[7:0]), .DIB(pci_ad[15:0]), .DOB() ); //ib write to registers always @(posedge ib_clock or posedge reset) if (reset) begin pci_base_addr <= 0; analyzer_run <= 0; end else begin if(ib_write_in) case(ib_addr) 11'h301: pci_base_addr[18:3] <= ib_data; 11'h302: pci_base_addr[2:0] <= ib_data[15:13]; 11'h303: analyzer_run <= ib_data[0]; default:; endcase end //ib read from registers always @(posedge ib_clock or posedge reset) if (reset) begin ib_addr_latch <= 11'h0; end else begin case(ib_addr) 'h300: data_out_latch <= {8'b0,capture_pci_addr}; 'h301: data_out_latch <= pci_base_addr[18:3]; 'h302: data_out_latch <= {pci_base_addr[2:0],13'b0}; 'h303: data_out_latch <= {15'b0,analyzer_run}; default:; endcase ib_addr_latch <= ib_addr; end assign ib_data = (ib_read_in & (ib_addr_latch[10:8]==3'h1)) ? ram_data_0 : 16'bz; assign ib_data = (ib_read_in & (ib_addr_latch[10:8]==3'h2)) ? ram_data_1 : 16'bz; assign ib_data = (ib_read_in & (ib_addr_latch[10:8]==3'h3)) ? data_out_latch : 16'bz; endmodule