`timescale 1ns / 1ps

// arbitrater for internal bus ownership
//	first-come first-served 
// in case of a tie, device 0 has priority
//

module arbitrator(req0, req1, gnt0, gnt1, clock, reset);
    input req0;
    input req1;
    output gnt0;
    output gnt1;
    input clock;
	 input reset;

reg gnt0;
reg gnt1;

always @(posedge clock or posedge reset)
	if(reset)
		begin
			gnt0 <= 0;
			gnt1 <= 0;
		end
	else
		begin
			gnt0 <= req0 & ~gnt1;
			gnt1 <= req1 & !req0 & ~gnt1;
		end
/*
assign gnt0 = req0;
assign gnt1 = req1;
*/

endmodule