`timescale 1ns / 1ps
/*//////////////////////////////////////////////////////////////////////////////
main device module. Connects PCI interface, USB interface, DAC controller, Reset 
generator to external circuits and to each other via internal bus. Also connects 
arbitrator for internal bus.

 
*///////////////////////////////////////////////////////////////////////////////
module fpga_top_level(AD, CBE, PCI_CLK, PCI_GNT_n, PCI_REQ_n, PME_n, IDSEL, FRAME_n, 
                    IRDY_n, TRDY_n, DEVSEL_n, STOP_n, LOCK_n, PERR_n, SERR_n, 
                    PAR, ACK64_n, REQ64_n, PCI_RESET_n, INTA_n,
						   
						  USB_PWREN_n, USB_SI_WU, USB_RXF_n,USB_TXE_n, USB_WR, 
						  USB_RD_n, USB_D, 

						  DACCLK, DAC, 

						  SRAM_A, SRAM_D, SRAM_OE_n, SRAM_UB_n, SRAM_LB_n, 
						  SRAM_CE_n, SRAM_WR_n, 

						  RESET_n, 
						  CLOCK1, CLOCK2,CLOCK3);
	//PCI signals
    inout [31:0] AD;
    inout [3:0] CBE;
    input PCI_CLK;
    inout PCI_GNT_n;
    inout PCI_REQ_n;
    input PME_n;
    input IDSEL;
    inout FRAME_n;
    inout IRDY_n;
    inout TRDY_n;
    inout DEVSEL_n;
    inout STOP_n;
    inout LOCK_n;
    inout PERR_n;
    output SERR_n;
    inout PAR;
    inout ACK64_n;
    input REQ64_n;
    input PCI_RESET_n;
    output INTA_n;

	 //USB signals
    input USB_PWREN_n;
    output USB_SI_WU;
    input USB_RXF_n;
	 input USB_TXE_n;
    output USB_WR;
    output USB_RD_n;
    inout [7:0] USB_D;

	 //DAC signals
    output DACCLK;
    output [15:0] DAC;

	 //External SRAM signals
    output [18:0] SRAM_A;
    inout [15:0] SRAM_D;
    output SRAM_OE_n;
    output SRAM_UB_n;
    output SRAM_LB_n;
    output SRAM_CE_n;
    output SRAM_WR_n;

	 //Reset pushbutton and other clocks.
	 input RESET_n;
	 input CLOCK1;
	 input CLOCK2;
	 input CLOCK3;


//internal bus signals
wire [15:0] ib_DATA;
wire [10:0] ib_ADDRESS;
wire ib_USB_READ;
wire ib_USB_WRITE;
wire ib_PCI_READ;
wire ib_PCI_WRITE;
wire ib_READ;
wire ib_WRITE;
wire ib_clock;
wire ib_pci_req;
wire ib_pci_gnt;
wire ib_usb_req;
wire ib_usb_gnt;

//for connection to USB chip
wire USB_RD;

wire manual_reset;

reg [0:4] slowclock;	//width of register determines clock speed: 5 bits is 50MHz/(2^5) ~1.5MHz

assign ib_READ  = ib_USB_READ  | ib_PCI_READ;
assign ib_WRITE = ib_USB_WRITE | ib_PCI_WRITE;


// synthesis attribute clock_signal of PCI_CLK_buf is “yes”;
wire PCI_CLK_buf;
assign PCI_CLK_buf = PCI_CLK & PCI_RESET_n; //stupid hack- should have used a GCLK input pin for PCI clock

pci_interface pci1(.AD(AD),
						.CBE(CBE),
						.PAR(PAR),
						.PCI_GNT_n(PCI_GNT_n),
						.PCI_REQ_n(PCI_REQ_n),
						.FRAME_n(FRAME_n),
						.IRDY_n(IRDY_n),
						.TRDY_n(TRDY_n),
						.DEVSEL_n(DEVSEL_n),
						.STOP_n(STOP_n),
						.IDSEL(IDSEL),
						.LOCK_n(LOCK_n),
						.PERR_n(PERR_n),
						.SERR_n(SERR_n),
						.ACK64_n(ACK64_n),
						.INTA_n(INTA_n),
						.PCI_RESET_n(PCI_RESET_n),
						.PCI_CLK(PCI_CLK_buf),
						.PME_n(PME_n),
						.REQ64_n(REQ64_n),

						.ib_req(ib_pci_req),
						.ib_gnt(ib_pci_gnt),
						.ib_write_out(ib_PCI_WRITE),
						.ib_read_out(ib_PCI_READ),
						.ib_write_in(ib_WRITE),
						.ib_read_in(ib_READ),
						.ib_data(ib_DATA),
						.ib_addr(ib_ADDRESS),
						.ib_clock(ib_clock));



//Clock generator for USB interface
//the interface generates lots of errors above 2MHz for unknown reasons
//this should be fixed although it doesn't really limit throughput.
always @ (posedge CLOCK2 or posedge manual_reset)
	if(manual_reset)
	slowclock <= 0;
	else
	slowclock <= slowclock+1;
// synthesis attribute clock_signal of slowclock[0] is “yes”;


dacdriver dac1(.data_out(DAC),
					.clock_out(DACCLK),
					.sram_data(SRAM_D),
					.sram_addr(SRAM_A),
					.sram_oe(SRAM_OE),
					.sram_rd(SRAM_RD),
					.sram_ce(SRAM_CE),
					.dac_clock_in(CLOCK2),
					.bus_clock_in(ib_clock),
					.ib_data(ib_DATA),
					.ib_addr(ib_ADDRESS),
					.ib_read(ib_READ),
					.ib_write(ib_WRITE),
					.reset(manual_reset));

arbitrator arb1(.req0(ib_pci_req),
					 .req1(ib_usb_req),
					 .gnt0(ib_pci_gnt),
					 .gnt1(ib_usb_gnt),
					 .clock(CLOCK2),
					 .reset(manual_reset));
// synthesis attribute clock_signal of ib_clock is “yes”;
assign ib_clock = (ib_pci_gnt & PCI_CLK) | (ib_usb_gnt & slowclock[0]);


assign USB_SI_WU = 1'b1;


assign USB_RD_n = ~USB_RD;
usb_interface usb1(.usb_data(USB_D),
						 .usb_txe(~USB_TXE_n),
						 .usb_rxf(~USB_RXF_n),
						 .usb_rd(USB_RD),
						 .usb_wr(USB_WR),
						 .ib_data(ib_DATA),
						 .ib_addr(ib_ADDRESS),
						 .ib_read(ib_USB_READ),
						 .ib_write(ib_USB_WRITE),
						 .ib_req(ib_usb_req),
						 .ib_gnt(ib_usb_gnt),
						 .clock(slowclock[0]),
						 .reset(manual_reset));
 
 //for testing the signals on the PCI bus. Never tested or used
analyzer analyzer1(.ib_data(ib_DATA), 
					.ib_addr(ib_ADDRESS), 
					.ib_read_in(ib_READ), 
					.ib_write_in(ib_WRITE), 
					.ib_clock(ib_clock), 
					.ib_pci_req(ib_pci_req),
					.pci_clock(PCI_CLK_buf), 
					.pci_ad(AD), 
					.pci_cbe(CBE), 
					.pci_trdy(TRDY_n), 
					.pci_irdy(IRDY_n), 
					.pci_frame(FRAME_n), 
					.pci_devsel(DEVSEL_n), 
               .pci_idsel(IDSEL), 
					.reset(manual_reset) 
				);

		
  
parameter bouncy = 1; //this parameter is for simulation purposes
							// it is overridden in pci_test_vector.v to shorten simulated startup time
wire debounced_reset;
debouncer reset_debounce(.signal_in(~RESET_n),
						.signal_out(debounced_reset),
						.clock(CLOCK2));
assign manual_reset = bouncy ? debounced_reset : ~RESET_n;


assign SRAM_OE_n = ~SRAM_OE;
assign SRAM_UB_n = 0;
assign SRAM_LB_n = 0;
assign SRAM_CE_n = ~SRAM_CE;
assign SRAM_WR_n = SRAM_RD;


endmodule