`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 23:33:04 04/09/06 // Design Name: // Module Name: pci_emulator // Project Name: // Target Device: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module pci_emulator(AD, CBE, FRAME_n, IRDY_n, TRDY_n, IDSEL, DEVSEL_n, PCI_CLK, PCI_RESET_n, strobe, read, mem,burst,address,data ); output [31:0] AD; output [3:0] CBE; output FRAME_n; output IRDY_n; input TRDY_n; output IDSEL; input DEVSEL_n; input PCI_CLK; input PCI_RESET_n; input strobe; input read; input mem; input [3:0] burst; input [29:0] address; input [31:0] data; reg [31:0] AD; reg [3:0] CBE; reg FRAME_n; reg IRDY_n; reg IDSEL; reg start_in; reg start; wire in_rst = ~PCI_RESET_n | start; always @( posedge strobe or posedge in_rst) if(in_rst) start_in <= 0; else start_in <= 1; always @( posedge PCI_CLK or negedge PCI_RESET_n) if(~PCI_RESET_n) start <= 0; else start <= start_in; reg read_s; reg mem_s; reg [3:0] burst_s; reg [3:0] burst_count; reg [31:0] address_s; reg [31:0] data_s; always @(posedge strobe or negedge PCI_RESET_n) if(~PCI_RESET_n) begin read_s <= 0; mem_s <= 0; address_s <= 0; data_s <= 0; burst_s <= 0; end else begin read_s <= read; mem_s <= mem; burst_s <= burst; address_s <= {address,2'b0}; data_s <= data; end reg [7:0] state; always @( posedge PCI_CLK or negedge PCI_RESET_n) if(~PCI_RESET_n) begin AD <= 32'bz; CBE <= 32'bz; FRAME_n <= 1; IRDY_n <= 1; IDSEL <= 0; state <= 0; burst_count <= 0; end else begin case(state) 0: begin AD <= 32'bz; CBE <= 32'bz; FRAME_n <= 1; IRDY_n <= 1; IDSEL <= 0; burst_count <= burst_s; if (start) case({read,mem}) 0: state <= 10; 1: state <= 20; 2: state <= 30; 3: state <= 40; endcase end 10: begin // config write FRAME_n <= 0; AD <= address_s; IDSEL <= 1; CBE <= 4'b1011; state <= state + 1; end 11: begin FRAME_n <= 1; AD <= data_s; CBE <= 4'hf; IRDY_n <= 0; state <= state + 1; end 12: begin IRDY_n <= 1; IDSEL <= 0; state <= state + 1; end 20: begin // mem write FRAME_n <= 0; AD <= address_s; CBE <= 4'b0111; state <= state + 1; end 21: begin FRAME_n <= (burst_count == 0); AD <= data_s + burst_count; CBE <= 4'hf; IRDY_n <= 0; burst_count <= burst_count - 1; state <= state + (burst_count == 0); end 22: begin IRDY_n <= 1; AD <= 32'bz; state <= state + 1; end 30: begin // config read FRAME_n <= 0; AD <= address_s; CBE <= 4'b1010; IDSEL <= 1; state <= state + 1; end 31: begin FRAME_n <= 1; AD <= 32'bz; CBE <= 4'hf; IRDY_n <= 0; state <= state + 1; end 32: state <= state + 1; 33: begin IRDY_n <= 1; IDSEL <= 0; state <= state + 1; end 40: begin // mem read FRAME_n <= 0; AD <= address_s; CBE <= 4'b0110; state <= state + 1; end 41: begin if(~|burst_s) FRAME_n <= 1; AD <= 32'bz; CBE <= 4'hf; IRDY_n <= 0; state <= state + (burst_count == 0); burst_count <= burst_count - 1; end 42: begin FRAME_n <= 1; state <= state + 1; end 43: begin IRDY_n <= 1; state <= state + 1; end default: state <= 0; endcase end endmodule