`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Test vector for simulating card. SRAM, USB chip and PCI interface are simulated
// DAC is ignored.
////////////////////////////////////////////////////////////////////////////////

module card_simulation_level;

	// Inputs
	reg PCI_CLK;
	reg PME_n;
	wire IDSEL;
	reg REQ64_n;
	reg PCI_RESET_n;
	wire USB_PWREN_n;
	wire USB_RXF_n;
	wire USB_TXE_n;	
	reg RESET_n;
	reg CLOCK1;
	reg CLOCK2;
	reg CLOCK3;

	// Outputs
	wire SERR_n;
	wire INTA_n;
	wire USB_SI_WU;
	wire USB_WR;
	wire USB_RD_n;

	wire DACCLK;
	wire [15:0] DAC;
	wire [18:0] SRAM_A;
	wire SRAM_OE_n;
	wire SRAM_UB_n;
	wire SRAM_LB_n;
	wire SRAM_CE_n;
	wire SRAM_WR_n;

	// Bidirs
	wire [31:0] AD;
	wire [3:0] CBE;
	wire PCI_GNT_n;
	wire PCI_REQ_n;
	wire FRAME_n;
	wire IRDY_n;
	wire TRDY_n;
	wire DEVSEL_n;
	wire STOP_n;
	wire LOCK_n;
	wire PERR_n;
	wire PAR;
	wire ACK64_n;
	wire [7:0] USB_D;
	wire [15:0] SRAM_D;
	
	reg strobe;
	reg read;
	reg mem;
	reg [3:0] burst;
	reg [29:0] address;
	reg [31:0] data;

	reg [7:0] usb_data;
	reg usb_strobe;

	// Instantiate the Unit Under Test (UUT)
	defparam uut.bouncy = 0;  //turn of reset debounce logic
	fpga_top_level uut (
		.AD(AD), 
		.CBE(CBE), 
		.PCI_CLK(PCI_CLK), 
		.PCI_GNT_n(PCI_GNT_n), 
		.PCI_REQ_n(PCI_REQ_n), 
		.PME_n(PME_n), 
		.IDSEL(IDSEL), 
		.FRAME_n(FRAME_n), 
		.IRDY_n(IRDY_n), 
		.TRDY_n(TRDY_n), 
		.DEVSEL_n(DEVSEL_n), 
		.STOP_n(STOP_n), 
		.LOCK_n(LOCK_n), 
		.PERR_n(PERR_n), 
		.SERR_n(SERR_n), 
		.PAR(PAR), 
		.ACK64_n(ACK64_n), 
		.REQ64_n(REQ64_n), 
		.PCI_RESET_n(PCI_RESET_n), 
		.INTA_n(INTA_n), 
		.USB_PWREN_n(USB_PWREN_n), 
		.USB_SI_WU(USB_SI_WU), 
		.USB_RXF_n(USB_RXF_n), 
		.USB_TXE_n(USB_TXE_n), 
		.USB_WR(USB_WR), 
		.USB_RD_n(USB_RD_n), 
		.USB_D(USB_D), 
		.DACCLK(DACCLK), 
		.DAC(DAC), 
		.SRAM_A(SRAM_A), 
		.SRAM_D(SRAM_D), 
		.SRAM_OE_n(SRAM_OE_n), 
		.SRAM_UB_n(SRAM_UB_n), 
		.SRAM_LB_n(SRAM_LB_n), 
		.SRAM_CE_n(SRAM_CE_n), 
		.SRAM_WR_n(SRAM_WR_n), 
		.RESET_n(RESET_n), 
		.CLOCK1(CLOCK1), 
		.CLOCK2(CLOCK2), 
		.CLOCK3(CLOCK3)
	);	
pci_emulator motherboard(
		.AD(AD), 
		.CBE(CBE), 
		.FRAME_n(FRAME_n),
		.IRDY_n(IRDY_n), 
		.TRDY_n(TRDY_n), 
		.IDSEL(IDSEL), 
		.DEVSEL_n(DEVSEL_n), 
      .PCI_CLK(PCI_CLK), 
		.PCI_RESET_n(PCI_RESET_n), 
		.strobe(strobe), 
		.read(read), 
		.mem(mem),
		.burst(burst),
		.address(address),
		.data(data)
	);
usb_emulator serialport(
		.USB_PWREN_n(USB_PWREN_n), 
		.USB_SI_WU(USB_SI_WU), 
		.USB_WR(USB_WR), 
		.USB_RD_n(USB_RD_n), 
		.USB_D(USB_D), 
		.USB_TXE_n(USB_TXE_n), 
		.USB_RXF_n(USB_RXF_n), 
		.USB_MASTER_WRITE(usb_strobe), 
		.USB_MASTER_DATA(usb_data), 
		.RESET(~RESET_n));

sram_emulator sram_chip(
		.data(SRAM_D), 
		.address(SRAM_A), 
		.oe_n(SRAM_OE_n), 
		.cs_n(SRAM_CE_n), 
		.wr_n(SRAM_WR_n), 
		.ub_n(SRAM_UB_n),
		.lb_n(SRAM_LB_n)
	);

	initial begin
		// Initialize Inputs
		PME_n = 0;
		REQ64_n = 0;
		PCI_RESET_n = 0;
		CLOCK1 = 0;
		CLOCK3 = 0;
		strobe = 0;
		read = 0;
		mem = 0;
		burst = 0;
		address = 0;
		data = 0;
		RESET_n = 0;
		#1 RESET_n = 1;

		/* begin PCI control */

		// Leave base address at 0;
		//#50 address = 4; data = 32'hffffffff;	  //set base address
		//#1 strobe = 1;	#1 strobe = 0;
	
	   #50 address = 1; data = 32'hffffffff; 	  //enable memory access
 		#1 strobe = 1;	#1 strobe = 0; 

 		#50 mem = 1; read = 0; address = 'h0; data = 32'h1; //request internal bus for pci
 		#1 strobe = 1;	#1 strobe = 0;

		#50 mem = 1; read = 0; address = 'h303; data = 32'h1; //start PCI logging
 		#1 strobe = 1;	#1 strobe = 0;

		//write 1,2,3,4 to ram buffer
		#50 read = 0; address = 'h400; data = 'h1;
 		#1 strobe = 1;	#1 strobe = 0;
 		#50 read = 0; address = 'h401; data = 'h2;
 		#1 strobe = 1;	#1 strobe = 0;
		#50 read = 0; address = 'h402; data = 'h3;
 		#1 strobe = 1;	#1 strobe = 0;
 		#50 read = 0; address = 'h403; data = 'h4;
 		#1 strobe = 1;	#1 strobe = 0;
  
  		#100 read = 0; address = 'h404; burst = 3; 
 		#1 strobe = 1;	#1 strobe = 0; burst = 0;

		//read ram contents back
		#50 read = 1;  
 		#1 strobe = 1;	#1 strobe = 0;
		#50 read = 1; address = 'h9; 
 		#1 strobe = 1;	#1 strobe = 0;

 		//set block length to 4
 		#50 read = 0; address = 'h9; data = 'h3;
  		#1 strobe = 1;	#1 strobe = 0;

		//read block length
		#50 read = 1; address = 'h9; 
 		#1 strobe = 1;	#1 strobe = 0;
		//start block write
		#50 read = 0; address = 'ha; data = 'h6; 
 		#1 strobe = 1;	#1 strobe = 0;

		//set block start to 0
  		#1000 read = 0; address = 'h7; data = 'h0;
  		#1 strobe = 1;	#1 strobe = 0;
 		//start block read
 		#50 read = 0; address = 'ha; data = 'h4; 
 		#1 strobe = 1;	#1 strobe = 0;

 		//read contents of block ram
		#1000 read = 1; address = 'h400; 
 		#1 strobe = 1;	#1 strobe = 0;
		#50 read = 1; address = 'h401; 
 		#1 strobe = 1;	#1 strobe = 0;
		#50 read = 1; address = 'h402; 	   
 		#1 strobe = 1;	#1 strobe = 0;
		#50 read = 1; address = 'h403; 
 		#1 strobe = 1;	#1 strobe = 0;

  		#100 read = 1; address = 'h400; burst = 3; 
 		#1 strobe = 1;	#1 strobe = 0; burst = 0;

  		  /* Begin USB control */
  /*
  		//write 0x01 and read from register 2 (test reg)
		#10 usb_strobe = 0; 
		#1 usb_data = {2'h3,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,2'h2,4'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h1}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#20;
		#1 usb_data = {2'h3,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h1,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,2'h2,4'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;

		//write 0x03 and read from DP ram 0 (0x400  - b'0100 000000 00)
 		#10 usb_strobe = 0; 
		#1 usb_data = {2'h3,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h4}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,2'h0,4'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h3}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#20;
		#1 usb_data = {2'h3,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h1,6'h4}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,2'h0,4'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
	
		//set block length 0x9: 7  (size 8)
		#10 usb_strobe = 0; 
		#1 usb_data = {2'h3,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h2}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,2'h1,4'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h7}; #1 usb_strobe = 1; #1 usb_strobe = 0;
	
		//start block write 0xa: 6
		#10 usb_strobe = 0; 
		#1 usb_data = {2'h3,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h2}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,2'h2,4'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h6}; #1 usb_strobe = 1; #1 usb_strobe = 0;
	
		//start block read 0xa: 4
		#10 usb_strobe = 0; 
		#1 usb_data = {2'h3,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h2}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,2'h2,4'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h0}; #1 usb_strobe = 1; #1 usb_strobe = 0;
		#1 usb_data = {2'h2,6'h4}; #1 usb_strobe = 1; #1 usb_strobe = 0;
	 */
	end
  



initial 
	PCI_CLK = 1'b0;
always
	#4 PCI_CLK = ~PCI_CLK;
initial 
	CLOCK2 = 1'b0;
always
	#3 CLOCK2 = ~CLOCK2;

initial
begin
	PCI_RESET_n = 0;
	RESET_n = 0;
	#20 PCI_RESET_n = 1;
	RESET_n = 1;
end
    
endmodule