`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    20:47:26 12/12/05
// Design Name:    
// Module Name:    sram_emulator
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module sram_emulator(data, address, oe_n, cs_n, wr_n, ub_n,lb_n);
    inout [15:0] data;
    input [18:0] address;
    input oe_n;
    input cs_n;
    input wr_n;
    input ub_n;
	 input lb_n;

parameter ADDRESS_BITS  = 3; 
/*number of address lines used*/
wire [18:0] address_d;
wire [15:0] data_d;

assign #1 address_d = address;
assign #1 data_d = data;

wire load;
wire read;
//reg [15:0] cells[1023:0];	 /* 512k 1<<19-1: 19 address bits*/
reg [15:0] cells[(1<<ADDRESS_BITS)-1:0];

assign load = ~cs_n & ~wr_n;
assign read = ~cs_n & ~oe_n/* & wr_n*/;

always @ (negedge load)
	cells[address_d[ADDRESS_BITS-1:0]] <= data_d;

//assign data = read ? cells[address[9:0]]:16'bz;
assign data = read ? cells[address[ADDRESS_BITS-1:0]]:16'bz;

endmodule