`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    16:48:32 12/12/05
// Design Name:    
// Module Name:    usb_emulator
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module usb_emulator(USB_PWREN_n, USB_SI_WU, USB_WR, USB_RD_n, USB_D, USB_TXE_n, 
                       USB_RXF_n, USB_MASTER_WRITE, USB_MASTER_DATA, RESET);
    output USB_PWREN_n;
    input USB_SI_WU;
    input USB_WR;
    input USB_RD_n;
    inout [7:0] USB_D;
    output USB_TXE_n;
    output USB_RXF_n;
    input USB_MASTER_WRITE;
    input [7:0] USB_MASTER_DATA;
	 input RESET;

reg [256*8-1:0] FIFO;
reg [7:0] in_ptr;
reg [7:0] out_ptr;

assign USB_TXE_n = 0;
assign USB_SI_WU = 0;
assign USB_PWREN_n = 0;

/*always @ (posedge reset or posedge USB_WR)
	if(reset)
		USB_TXE_n = 0;
	else
*/
		
always @ (posedge RESET or posedge USB_MASTER_WRITE)
	if(RESET)
	begin
		FIFO <= 0;
		in_ptr <= 0;
	end
	else
	begin
		in_ptr <= in_ptr + 1;
		FIFO <= ( FIFO & ~(8'b1111_1111 << (in_ptr * 8))) | (USB_MASTER_DATA << (in_ptr * 8));
	end

always @ (posedge RESET or posedge USB_RD_n)
	if(RESET)
	out_ptr <= 0;
	else
	out_ptr <= out_ptr + 1;

assign USB_D = ~USB_RD_n ? (FIFO>>out_ptr*8) & 8'b1111_1111 : 8'bz;

assign USB_RXF_n = (out_ptr == in_ptr);
endmodule